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the information contained in this document is being issued in advance of the production cycle for the device. the parameters for the device may change before final production or nec corporation, at its own discretion, may withdraw the device prior to its production. not all devices/types available in every country. please check with local nec representative for availability and additional information. ? 2002 mos integrated circuit pd161831 240/244-output tft-lcd source driver with timing generator (compatible with 64-gray scales) preliminary product information document no. s16269ej2v0pm00 (2nd edition) date published october 2002 ns cp (k) printed in japan the mark shows major revised points. description the pd161831 is a source driver for lips tfts with on-chip timing generator and featuring 240/244 outputs. data input as 6-bit x 3-dot digital data is output as 64 -corrected values using an internal d/a converter, achieving 260,000-color (full-color) display. features ? cmos level input ? 240/244 outputs (r, g, b output) ? input of 6 bits (gray-scale data) by 3 dots ? capable of outputting 64 values by means of 5 external power modules and a d/a converter ? output dynamic range: v ss + 0.05 v to v s ? 0.05 v ? high-speed data transfer: f clk = 20 mhz max. (during 2-times data transfer when operating at v cc = 2.5 v. during 1-time data transfer 10 mhz max.) ? high-speed data transfer: f clk = 16 mhz max. (during 2-times data transfer when operating at v cc = 2.2 v. during 1-time data transfer 8 mhz max.) ? on-chip power supplies (driver power supply, gate top power supply, gate bottom power supply) ? logic power supply voltage (v cc ): 2.2 to 3.6 v ? dc/dc reference power supply (v dc ): 2.5 to 3.6 v ? on-chip timing generator (outputs r, g, b switching signal to panel. outputs gate control signal.) ? on-chip 8-bit serial interface (applied to spi) ordering information part number package pd161831p chip remark purchasing the above chip entail the exchange of documents such as a separate memorandum or product quality, so please contact one of our sales representatives.
preliminary product information s16269ej2v0pm 2 pd161831 1. block diagram sclk si so lcdcs scleg0 scleg1 /cs1 cs2 sclk_sub so_sub a0 serial interface rgb interface d00-d05 d10-d15 d20-d25 dck cks gate control multiplex switch control rsw_o gsw_o bsw_o ext1_o ext2_o ext3_o l/s l/s gclk_o gstb_o goe1_o goe2_o gr,/l_o control gam v0-v4 bias control command decoder 244-bit bidirectional shift register timing controler vcom buffer data register data latch level shifter d/a converter output buffer testout testin2 testin1 hsync vsync /reset mas,/slv comdcin comdcsl comdc comc vcomh s1 s244 vcc vss1 vdc dc/dc converter dc/dc converter c1+/ ? c2+/ ? c3+/ ? c5+/ ? c4+/ ? osc dcclk vdc2 vdd2 vss1 vr vs vref vdc vgd vdd2 vss2/3 vdd2 vss2/3 rgb sw vss2 rsw_i gsw_i bsw_i ext1_i ext2_i ext3_i gclk_i gstb_i goe1_i goe2_i sthr sthl data latch control pol ap stb tcon hseg vseg test_com2 test_vclamp testin4 testin3 pvss bgr_o pvcc remark /xxx indicates active low si gnal.
preliminary product information s16269ej2v0pm 3 pd161831 2. pin configuration (pad layout) chip size: t.b.d. bump size: input/vcom/test/dummy: 50 x 75 m 2 output: 35 x 100 m 2 remark t.b.d.: to be determined . alignment mark (unit: m) x coordinate y coordinate aluminum (core) 10768.0 441.0 alignment1 bump (core) 10768.0 366.0 aluminum (core) ? 10768.0 441.0 alignment2 bump (core) ? 10768.0 366.0 remark the figures are rounded off in 0.5 m units. alignment2 alignment1 driver output side input/output side alminum bump 50 m 50 m 50 m 50 m
preliminary product information s16269ej2v0pm 4 pd161831 table 2?1. pad layout (1/2) no. pad name x [
preliminary product information s16269ej2v0pm 5 pd161831 table 2?1. pad layout (2/2) no. pad name m] y [ m] no. pad name x [ m] y [ m] no. pad name x [ m] y [ m] no. pad name x [ m] y [ m] 281 dummy -6780.00 594.99 351 vdc -7880.04 -607.50 421 dummy -2080.26 -607.50 491 d25 4594.17 -607.50 282 dummy -6840.00 594.99 352 vdc2 -7780.05 -607.50 422 dummy -1980.27 -607.50 492 d24 4694.16 -607.50 283 bsw_o -6900.00 594.99 353 vdc2 -7705.05 -607.50 423 dummy -1880.28 -607.50 493 d23 4794.15 -607.50 284 bsw_o -6960.00 594.99 354 vdc2 -7630.05 -607.50 424 dummy -1780.29 -607.50 494 d22 4894.14 -607.50 285 gsw_o -7080.00 594.99 355 vdc2 -7555.05 -607.50 425 dummy -1680.30 -607.50 495 d21 4994.13 -607.50 286 gsw_o -7140.00 594.99 356 vdc2 -7480.05 -607.50 426 dummy -1580.31 -607.50 496 d20 5094.12 -607.50 287 rsw_o -7260.00 594.99 357 vdc2 -7405.05 -607.50 427 vcc -1480.32 -607.50 497 d15 5194.11 -607.50 288 rsw_o -7320.00 594.99 358 vdc2 -7330.05 -607.50 428 vcc -1405.32 -607.50 498 d14 5294.10 -607.50 289 ext3_o -7440.00 594.99 359 c1+ -7230.06 -607.50 429 vcc -1330.32 -607.50 499 d13 5394.09 -607.50 290 ext3_o -7500.00 594.99 360 c1+ -7155.06 -607.50 430 vcc -1255.32 -607.50 500 d12 5494.08 -607.50 291 ext2_o -7620.00 594.99 361 c1+ -7080.06 -607.50 431 vss -1155.33 -607.50 501 d11 5594.07 -607.50 292 ext2_o -7680.00 594.99 362 c1+ -7005.06 -607.50 432 vss -1080.33 -607.50 502 d10 5694.06 -607.50 293 ext1_o -7800.00 594.99 363 c1+ -6930.06 -607.50 433 vss -1005.33 -607.50 503 d05 5794.05 -607.50 294 ext1_o -7860.00 594.99 364 c1+ -6855.06 -607.50 434 vss -930.33 -607.50 504 d04 5894.04 -607.50 295 vss2 -7980.00 594.99 365 c1+ -6780.06 -607.50 435 vss -855.33 -607.50 505 d03 5994.03 -607.50 296 vss2 -8040.00 594.99 366 c1- -6680.07 -607.50 436 sthr -755.34 -607.50 506 d02 6094.02 -607.50 297 vss2 -8100.00 594.99 367 c1- -6605.07 -607.50 437 goe2_i -655.35 -607.50 507 d01 6194.01 -607.50 298 vss2 -8160.00 594.99 368 c1- -6530.07 -607.50 438 goe1_i -555.36 -607.50 508 d00 6294.00 -607.50 299 vss1 -8280.00 594.99 369 c1- -6455.07 -607.50 439 gstb_i -455.37 -607.50 509 sthl 6393.99 -607.50 300 vss1 -8340.00 594.99 370 c1- -6380.07 -607.50 440 gclk_i -355.38 -607.50 510 sthl 6468.99 -607.50 301 vss1 -8400.00 594.99 371 c1- -6305.07 -607.50 441 stb -255.39 -607.50 511 testout 6568.98 -607.50 302 vss1 -8460.00 594.99 372 c1- -6230.07 -607.50 442 ap -155.40 -607.50 512 testin4 6668.97 -607.50 303 vdd2 -8580.00 594.99 373 c2+ -6130.08 -607.50 443 pol -55.41 -607.50 513 testin3 6768.96 -607.50 304 vdd2 -8640.00 594.99 374 c2+ -6055.08 -607.50 444 tcon 44.58 -607.50 514 testin2 6868.95 -607.50 305 vdd2 -8700.00 594.99 375 c2+ -5980.08 -607.50 445 pvcc 144.57 -607.50 515 testin1 6968.94 -607.50 306 vdd2 -8760.00 594.99 376 c2+ -5905.08 -607.50 446 osel 244.56 -607.50 516 v4 7068.93 -607.50 307 goe2_o -8880.00 594.99 377 c2+ -5830.08 -607.50 447 vcsel 344.55 -607.50 517 v4 7143.93 -607.50 308 goe2_o -8940.00 594.99 378 c2+ -5755.08 -607.50 448 gam 444.54 -607.50 518 v3 7243.92 -607.50 309 goe2_o -9000.00 594.99 379 c2+ -5680.08 -607.50 449 mas/slv 544.53 -607.50 519 v3 7318.92 -607.50 310 goe2_o -9060.00 594.99 380 c2- -5580.09 -607.50 450 scleg1 644.52 -607.50 520 v2 7418.91 -607.50 311 goe1_o -9180.00 594.99 381 c2- -5505.09 -607.50 451 scleg0 744.51 -607.50 521 v2 7493.91 -607.50 312 goe1_o -9240.00 594.99 382 c2- -5430.09 -607.50 452 cks 844.50 -607.50 522 v1 7593.90 -607.50 313 gr/l_o -9360.00 594.99 383 c2- -5355.09 -607.50 453 hseg 944.49 -607.50 523 v1 7668.90 -607.50 314 gr/l_o -9420.00 594.99 384 c2- -5280.09 -607.50 454 vseg 1044.48 -607.50 524 v0 7768.89 -607.50 315 gclk_o -9540.00 594.99 385 c2- -5205.09 -607.50 455 pvss 1144.47 -607.50 525 v0 7843.89 -607.50 316 gclk_o -9600.00 594.99 386 c2- -5130.09 -607.50 456 ext3_i 1244.46 -607.50 526 dummy 7943.88 -607.50 317 gstb_o -9720.00 594.99 387 c3+ -5030.10 -607.50 457 ext2_i 1344.45 -607.50 527 dummy 8043.87 -607.50 318 gstb_o -9780.00 594.99 388 c3+ -4955.10 -607.50 458 ext1_i 1444.44 -607.50 528 dummy 8143.86 -607.50 319 dummy -9840.00 594.99 389 c3+ -4880.10 -607.50 459 bsw_i 1544.43 -607.50 529 dummy 8243.85 -607.50 320 dummy -10677.00 594.99 390 c3- -4780.11 -607.50 460 gsw_i 1644.42 -607.50 530 dummy 8343.84 -607.50 321 dummy -10737.00 594.99 391 c3- -4705.11 -607.50 461 rsw_i 1744.41 -607.50 531 dummy 8443.83 -607.50 322 dummy -10797.00 594.99 392 c3- -4630.11 -607.50 462 dummy 1844.40 -607.50 532 dummy 8543.82 -607.50 323 dummy -10788.00 -607.50 393 c4+ -4530.12 -607.50 463 dummy 1944.39 -607.50 533 comdcsl 8643.81 -607.50 324 dummy -10688.01 -607.50 394 c4+ -4455.12 -607.50 464 dummy 2044.38 -607.50 534 comdcin 8743.80 -607.50 325 dummy -10588.02 -607.50 395 c4+ -4380.12 -607.50 465 dummy 2144.37 -607.50 535 comdcin 8818.80 -607.50 326 dummy -9879.99 -607.50 396 c4- -4280.13 -607.50 466 dummy 2244.36 -607.50 536 vcomh 8918.79 -607.50 327 vss -9780.00 -607.50 397 c4- -4205.13 -607.50 467 /reset 2344.35 -607.50 537 vcomh 8993.79 -607.50 328 vss -9705.00 -607.50 398 c4- -4130.13 -607.50 468 a0 2444.34 -607.50 538 vcomh 9068.79 -607.50 329 vss -9630.00 -607.50 399 c5+ -4030.14 -607.50 469 cs2 2544.33 -607.50 539 vcomh 9143.79 -607.50 330 vss -9555.00 -607.50 400 c5+ -3955.14 -607.50 470 cs1 2644.32 -607.50 540 comdc 9243.78 -607.50 331 vss -9480.00 -607.50 401 c5+ -3880.14 -607.50 471 sclk_sub 2744.31 -607.50 541 comdc 9318.78 -607.50 332 vs -9380.01 -607.50 402 c5- -3780.15 -607.50 472 sosub 2844.30 -607.50 542 comc 9418.77 -607.50 333 vs -9305.01 -607.50 403 c5- -3705.15 -607.50 473 lcdcs 2944.29 -607.50 543 comc 9493.77 -607.50 334 vs -9230.01 -607.50 404 c5- -3630.15 -607.50 474 lcdcs 3019.29 -607.50 544 comc 9568.77 -607.50 335 vs -9155.01 -607.50 405 dcclk -3530.16 -607.50 475 sclk 3119.28 -607.50 545 comc 9643.77 -607.50 336 vs -9080.01 -607.50 406 vdd2 -3430.17 -607.50 476 sclk 3194.28 -607.50 546 comc 9718.77 -607.50 337 vgd -8980.02 -607.50 407 vdd2 -3355.17 -607.50 477 si 3294.27 -607.50 547 dummy 9818.76 -607.50 338 vgd -8905.02 -607.50 408 vss1 -3255.18 -607.50 478 si 3369.27 -607.50 548 dummy 10588.02 -607.50 339 vgd -8830.02 -607.50 409 vss1 -3180.18 -607.50 479 so 3469.26 -607.50 549 dummy 10688.01 -607.50 340 vgd -8755.02 -607.50 410 vss2 -3080.19 -607.50 480 so 3544.26 -607.50 550 dummy 10788.00 -607.50 341 vr -8655.03 -607.50 411 vss2 -3005.19 -607.50 481 vsync 3644.25 -607.50 342 vr -8580.03 -607.50 412 test_vclamp -2905.20 -607.50 482 hsync 3744.24 -607.50 343 vr -8505.03 -607.50 413 test_vclamp -2830.20 -607.50 483 hsync 3819.24 -607.50 344 vr -8430.03 -607.50 414 test_com2 -2730.21 -607.50 484 dck 3919.23 -607.50 345 vdc -8330.04 -607.50 415 test_com2 -2655.21 -607.50 485 dck 3994.23 -607.50 346 vdc -8255.04 -607.50 416 bgr_o -2555.22 -607.50 486 dummy 4094.22 -607.50 347 vdc -8180.04 -607.50 417 mvs -2455.23 -607.50 487 dummy 4194.21 -607.50 348 vdc -8105.04 -607.50 418 mvs -2380.23 -607.50 488 dummy 4294.20 -607.50 349 vdc -8030.04 -607.50 419 dummy -2280.24 -607.50 489 dummy 4394.19 -607.50 350 vdc -7955.04 -607.50 420 dummy -2180.25 -607.50 490 dummy 4494.18 -607.50
preliminary product information s16269ej2v0pm 6 pd161831 3. pin functions 3.1 source driver control pins (1/2) pin symbol pin name pin number i/o description s 1 to s 244 driver output 248 to 5 output the d/a converted 64-gray-scale analog voltage is output. osel = l: s 1 to s 244 osel = h: s 3 to s 242 osel driver output count switching 446 input the output count can be selected. when osel = h, the unused pins s 1 , s 2 , s 243 , s 244 always become hi-z (high impedance). osel = l: 244 outputs osel = h: 240 outputs dck dot clock 484, 485 input dot clock signal cks dot clock inversion 452 input inverts the active level of the dot clock. cks = l: low active cks = h: high active hsync horizontal sync signal 482, 483 input horizontal sync signal input pin. do not input a width wider than the horizontal period as the width of the hsync active level. vsync vertical sync signal 481 input vertical sync signal input pin. hseg hsync polarity selection 453 input selects the active level of the hsync signal. hseg = l: low active hseg = h: high active vseg vsync polarity selection 454 input selects the active level of the vsync signal. vseg = l: low active vseg = h: high active d 00 to d 05 508 to 503 d 10 to d 15 502 to 497 d 20 to d 25 display data input 496 to 491 input the display data is input with a width of 18 bits, the gray scale data (6 bits) by 3 dots (1 pixels). d x0 : lsb, d x5 : msb sclk serial clock input 475, 476 input clock pin of serial interface. so serial data output 479, 480 output data output pin of serial interface. si serial data input 477, 478 input data input pin of serial interface. lcdcs serial interface chip select 473, 474 input chip select pin of serial interface. scleg0, scleg1 serial clock mode selection 451, 450 input mode select pin of serial clock. for details, refer to 4. registers for explanation in serial interface . vcsel com amplitude output fixing signal 447 input fixes the vcom output to l. when not using the vcom output, set vcsel to l. vcsel = l: vcom output fixed to l vcsel = h: vcom signal output in accordance with pol signal gam external -usage selection 448 input when the -correction power supply is input externally, switch gam to h. if two or more chips are used, be sure to input the - correction power supply externally. figure 3 ? 1 shows vcom application example. gam = l: external -correction power supply not input gam = h: external -correction power supply input
preliminary product information s16269ej2v0pm 7 pd161831 (2/2) pin symbol pin name pin name i/o description mas, /slv master slave control 449 input when the timing generator is used and 2 chips are connected in cascade, selects use either as master ic or slave ic. when the timing generator is not used, either leave this pin or input a high level. mas, /slv = l: use as slave mas, /slv = h: use as master v 0 -v 4 -corrected power supplies 525 to 516 input these pins input the -corrected power supplies from outside, the relationship below must be observed. also, be sure to stabilize the gray-scale-level power supply during gray-scale voltage output. v ss v 4 v 3 v 2 v 1 v 0 v s vcomh amplitude voltage 536 to 539 output outputs the voltage set with the amplitude voltage adjustment d/a converter. comc square wave signal output 542 to 546 output outputs the square wave signal obtained through common modulation of v p-p voltage 0 v-vcomh. comdc common center voltage output 540, 541 output outputs the common center voltage. comdcin common center voltage external input 534, 535 input input pin used to input the common center voltage from external. valid when comdcsl = h. comdcsl common center voltage external input switch 533 input inputs a h level as the common voltage when the voltage input from the comdcin pin is used. tcon timing generator use/non-use selection 444 input this pin is used to select whether or not to use the timing generator. tcon = l: timing generator used tcon = h: timing generator not used /reset reset 467 input reset pin. this is the active low signal. figure 3 ? ? ? ? 1. vcom application example 4.7 f comc v s comdc 4 bit dac r = 460 k ? to 920 k ? comh (3:0) register vcomh [(34/50) v s to (49/50) v s ] com pol v s v s r-strings 7 bit dac comm (6:0) register v s comdcin comdcsl 0.6 v s (v) (1/50) v s step
preliminary product information s16269ej2v0pm 8 pd161831 3.2 gate scan control pins pin symbol pin name pin name i/o description gclk_o gate clk output 315, 316 output pin for clk output to the gate control circuit. gstb_o gate stb output 317, 318 output pin for strobe signal fed to gate control circuit goe1_o gate oe1 output 311, 312 output pin for oe1 output to gate control circuit goe2_o gate oe2 output 307 to 310 output pin for oe2 output to gate control circuit gclk_i gate clk input 440 input input the clk signal to the gate control circuit, when the timing generator function is not used. the signal input to this pin is output from the gclk_o via a level shifter. gstb_i gate stb input 439 input input the stb signal to the gate control circuit, when the timing generator function is not used. the signal input to this pin is output from the gstb_o via a level shifter. goe1_i gate oe1 input 438 input input the oe1 signal to the gate control circuit, when the timing generator function is not used. the signal input to this pin is output from the goe1_o via a level shifter. goe2_i gate oe2 input 437 input input the oe2 signal to the gate control circuit, when the timing generator function is not used. the signal input to this pin is output from the goe2_o via a level shifter. gr,/l_o gate r,/l output 313, 314 output pin that outputs r,/l to the gate control circuit. 3.3 control pin for multiplex switch, etc. pin symbol pin name pin name i/o description rsw_o 287, 288 output gsw_o 285, 286 output bsw_o multiplex control signal output 283, 284 output output pin that controls the multiplex switch on the panel. ext1_o 293, 294 output ext2_o 291, 292 output ext3_o extension control signal output 289, 290 output extension output pin that controls the circuit on the panel. rsw_i 461 input pin for inputting the signal that controls the multiplex switch on the panel, when the timing generator function is not used. the signal input to this pin is output from the rsw_o pin via a level shifter. gsw_i 460 input pin for inputting the signal that controls the multiplex switch on the panel, when the timing generator function is not used. the signal input to this pin is output from the gsw_o pin via a level shifter. bsw_i multiplex control signal input 459 input pin for inputting the signal that controls the multiplex switch on the panel, when the timing generator function is not used. the signal input to this pin is output from the bsw_o pin via a level shifter. ext1_i 458 input pin for inputting the extension signal that controls the circuit on the panel, when the timing generator function is not used. the signal input to this pin is output from the ext1_o pin via the level shifter. ext2_i 457 input pin for inputting the extension signal that controls the circuit on the panel, when the timing generator function is not used. the signal input to this pin is output from the ext2_o pin via the level shifter. ext3_i extension control signal input 456 input pin for inputting the extension signal that controls the circuit on the panel, when the timing generator function is not used. the signal input to this pin is output from the ext3_o pin via the level shifter.
preliminary product information s16269ej2v0pm 9 pd161831 3.4 power supply function control pin pin symbol pin name pin name i/o description c1+/ ? ,c2+/ ? , c3+/ ? ,c4+/ ? , c5+/ ? booster capacitor connection 359 to 404 ? connect the boost capacitor of the dc/dc converter to this pin. booster ratio is difference on the way of using condenser connection. for details, refer to figure 3 ? 3. v dc2 dc/dc converter output 352 to 358 ? dc/dc converter boost output (v dc x 2 or v dc x 3). this output is the v s and v r amplifier power supply. the v dc2 boot step is selected with the v cd2 bit. v cd2 bit = 0: v dc x 2 v cd2 bit = 1: v dc x 3 v s source power supply output 336 to 332 ? source voltage output pin. the v s output voltage can be changed through the vsel0 to vsel2. mv s external resistance input 417, 418 input an external resistance can be input to set any output voltage. exrv bit = 0: leave open (internal resistor selection) exrv bit = 1: connect external resistor. v r reference power supply output 341 to 344 ? gate reference power supply output pin. the v r output voltage can be changed through the vrsel to vrsel2 setting. v dd2 dc/dc converter output 303 to 306, 406, 407 ? dc/dc converter boost output (v gd x 2) v ss1 dc/dc converter output 299 to 302, 408 to 411 ? dc/dc converter boost output (v gd x ? 1) v ss2 dc/dc converter output 295 to 298 ? dc/dc converter boost output (v gd x ? 2) v dc reference power supply input for source power supply voltage 345 to 351 ? extension pin used to control circuit on panel. v gd reference power supply input for gate power supply voltage 337 to 340 ? extension pin used to control circuit on panel. dcclk boost clock input 405 input pin used to input boost clock of dc/dc converter. figure 3 ? ? ? ? 2. dc/dc converter boost configuration v dc2 : v dc x 2 or v dc x 3 regulator outputs v r and v s are generated from v dc2 . the following voltages can be selected for v s and v r . 3.0 v, 3.5 v, 4.0 v, 4.5 v, 4.75 v, 5.0 v, 5.25 v, 5.5 v v ss1 : v r x ? 1 or v s x ? 1 v dc : 2.5 to 3.6 v v ss : 0 v v ss2 : v r x ? 2 or v s x ? 2 v r , v s v dd2 : v r x 2 or v s x 2 v cc : 2.5 to 3.6 v
preliminary product information s16269ej2v0pm 10 pd161831 figure 3 ? ? ? ? 3. relationship between condenser connection for booster and booster ratio c5+ c5- c4+ c4- c3+ c3- c2+ c2- c1+ c1- v dc2 = v dc x 3 c2+ c2- c1+ c1- c2+ c2- c1+ c1- v dd1 v ss1 v ss2 c5+ c5- c4+ c4- c3+ c3- v ss1 v ss2 c5+ c5- c4+ c4- c3+ c3- v ss1 v ss2 c5+ c5- c4+ c4- c3+ c3- v ss1 v ss2 v dc2 = v dc x 2 v dc2 = v dc x 2 (dual mode) v dd2 = v gd x 3 v ss1 = v gd x ? 2 v ss2 = v gd x ? 3 v dd2 (single mode) v dd2 = v gd x 3 v ss1 = ? v ss2 = v gd x ? 2 v dd2 = v gd x 2 v ss1 = v gd x ? 1 v ss2 = v gd x ? 2 v dd2 v dd2 v dd2 = v gd x 2 v ss1 = ? v ss2 = v gd x ? 1 v dd1 v dd1 v dd1 figure 3 ? ? ? ? 4. v s , amp. circuit configuration r bs r as c3 4 v, 5 v mv s r cs v ref v dc2 ? + c3 v s c3 mv s v ref v dc2 + c3 r bs r as internal resistor mode exrv = l external resistor mode exrv = h v s =(1+ )v ref r bs r as testout1 testout1 ? 4 v, 5 v
preliminary product information s16269ej2v0pm 11 pd161831 3.5 control pins when timing generator function not used, and other pins pin symbol pin name pin name i/o description sthr right shift start pulse i/o 436 i/o start pulse i/o pin during cascade connection. when an h level is read at the rising edge of clk, fetching of display data starts. sthl left shift start pulse i/o 509, 510 i/o in the case of right shift, sthr = input and sthl = output. in the case of left shift, sthl = input and sthr = output. stb latch input 441 input this is the timing signal at which the contents of the data register are latched. when an h level is read at the rising edge of clk, the contents of the data register are latched and transferred to the d/a converter, and an analog voltage is output according to the display data. even after stb fetch, do not stop clk because the internal operation is performed using clk. at the rising edge of stb, the content of the shift register are cleared. after one pulse is input at startup, the operation becomes normal. at the rising edge of stb, the output switch is switched off. for the stb input timing, refer to 5. timing generator non-use function. ap output sw on/off 442 input switches the bias circuit on/off and the output switch and amplifier on. the period during which ap is h is the amplifier circuit setting period and the liquid crystal drive period. at the falling edge of ap, the amplifier output and output switch go on and liquid crystal driving starts. at the rising edge of stb, the output switch is switched to off ad the output becomes hi-z. pol polarity inversion signal 443 input inverts the output polarity. at the siring edge of rsel, the polarity inversion signal data is fetched internally. the - resistor is switched according to the positive and negative polarity. pol = l: negative polarity (common high output) pol = h: positive polarity (common low output) 3.6 back panel lcd controller driver control pins pin symbol pin name pin name i/o description /cs1 back panel lcd chip select 470 output active-low chip select signal to the back panel lcd controller driver. cs2 back panel lcd chip select 469 output active-high chip select signal to the back panel lcd controller driver. sclk_sub serial clock to the back panel lcd 471 output back panel lcd serial data output. so_sub outputs serial data to the back panel lcd 472 output outputs serial data to the back panel lcd controller driver. a0 back panel lcd data/command control 468 output controls data/command to the back panel lcd controller driver.
preliminary product information s16269ej2v0pm 12 pd161831 3.7 other control pins pin symbol pin name pin name i/o description testin1 to testin4 test input 515 to 512 input keep this pin low-level or leave it open. testout test output 511 output leave this pin open. test_com2 test output 414, 415 output leave this pin open. test_vclamp test output 412, 413 output leave this pin open. bgr_o hand cap regulator output 416 output leave this pin open. pv cc power supply for pull-up 445 ? this is pull-up power supply for mode setting pin. pv ss power supply for pull-down 456 ? this is pull-down power supply for mode setting pin. v cc logic supply voltage 427 to 430 ? 2.2 to 3.6 v v ss driver ground 327 to 331. 431 to 435 ? grounding dummy dummy 1 to 4, 249 to 282, 319 to 326, 419 to 426, 462 to 466, 486 to 490, 526 to 532 ? dummy pin caution to avoid latch-up failure, the sequence when turning on the power must be v cc logic input booster voltage for rising gray-scale power supply (v 0 -v 4 ), and the reverse sequence when turning off the power. follow this sequence during shift periods as well.
preliminary product information s16269ej2v0pm 13 pd161831 4. registers the pd161831 can set a horizontal period and vertical period by using registers. the serial interface is used to specify a register and set values to it. figure 4 ? 1 shows a simplified timing chart of the serial interface. figure 4 ? ? ? ? 1. timing chart of serial interface a7 a6 a5 a4 a3 a2 a1 a0 lcdcs si sclk d7 d6 d5 d4 d3 d2 d1 d0 serial interface operation specification transfer - specification of register - specification of read or write - selection of back panel lcd function - selection of serial interface for gate command & data transfer - selection of command register - transfer of set values of command register this serial interface has an 8-bit configuration. note that it is accessed twice in 8-bit units to set a register. the first 8-bit data (a7 to a0 in figure 4 ? 1) is transferred to the ?serial interface operation specification register?. the serial interface operation specification register specifies the transfer operation of the next 8 bits (d7 to d0 in figure 4 ? 1). the second 8-bit data selects a command register or transfers the set value of the command register. in addition, while writing a setup in command register with the 8-bit transfer + 8-bit (a7 to a0 + d7 to d0) which selects command register or transferring of 8 bit + 8-bit transfer of readings (a7 to a0 + d7 to d0) (a total of 32 bits), continue making chip select (lcdcs) active. table 4 ? 1 indicates the function of the serial interface operation specification register. table 4 ? 2 shows the register number and register name of each command register. tables 4 ? 3 and 4 ? 5 to 4 ? 24 describe the function of each command register. when the timing generator is used, there are three execution patterns for each command: immediate execution following setting, execution at the line following that where command was set, and execution at the frame following that where command was set. in the case of execution at the next line and execution at the next frame, the concrete command execution timing is as follows. however, when the timing generator is not used, commands are executed at the first falling edge of dck following command transmission. hsync hsync dotclk vsync dotclk dotclk dotclk <1> <2> <3> <4> <1> <2> <3> <4> execution from next line following command input (hsync, dotclk = low active) command input in above interval is executed at the next line. command execution execution from next frame following command input (vsync, hsync, dotclk = low active) <1> <2> <3> <4> <1> <2> <3> <4> command input in above interval is executed at the next line. command execution
preliminary product information s16269ej2v0pm 14 pd161831 4.1 serial interface operation specification register table 4 ? 1 shows the function of the serial interface operation specification register. table 4 ? ? ? ? 1. function of serial interface operation specification register (a7 to a0) no. bit name function a7 ?? a6 pd161831/back panel lcd select this bit specifies whether data d7 to d0 are data for a register of the pd161831 or data for the back panel lcd. if d7 to d0 are data for the back panel lcd, the chip select pins for the back panel lcd (/cs1 = l, cs2 = h) are asserted, and data d7 to d0 are output to sub_so along with the clock output by sclk_sub. 0: d7 to d0 are data for a pd161831 register. 1: d7 to d0 are data for the back panel lcd controller driver. a5 read/write select this bit selects whether the transfer of data d7 to d0 is for a read operation or a write operation. note, however, that in a read operation, only the registers of the pd161831 can be read. for the timing chart of the read operation, refer to 5. timing generator non-use function . 0: d7 to d0 are for a write operation. 1: d7 to d0 are for a read operation. a4 ?? a3 ?? a2 ?? a1 ?? a0 command/data select this bit selects whether data d7 to d0 specify the register number of a command register or are set to a command register. if an access to the back panel lcd controller driver is selected (a6 = 1), the value of this bit is reflected on the a0 pin (when a0 = 0: low output, when a0 = 1: high output). 0: d7 to d0 specify a register number. 1: d7 to d0 are set to a register.
preliminary product information s16269ej2v0pm 15 pd161831 4.2 command registers 4.2.1 command register list table 4 ? 2 lists the command registers. however, each register is read default value when invalid data leads in unused of timing generator. table 4 ? ? ? ? 2. command register list (1/2) d5 to d0 timing generator function reset register no. d5 d4 d3 d2 d1 d0 register name default value use not used command hard internal set timing r0 00000065, 000/260,000 color select 00h o ? o ? f r1 000001 horizontal period valid data input start timing 0ah o ? o ? f r2 000010 vertical period valid data input start timing 02h o ? o ? f r3 000011horizontal valid pixel data setting 00h o ? o ? c r4 000100st andby 00h o o o ? f r5 0001018-color mode 00h o o o ? l r6 000110setting 02h o ? 1o note1 note2 r7 ?????? use prohibited (not used) ????? ? r8 001000 amplifier drive period setting 0eh o ? o ? c r9 001001quarter data function 00h o o o ? f r10 001011level shifter volt age setting 00h o o o ? c r11 001100 common amplitude voltage adjustment d/a converter 0fhooo ? c r12 001101 common center voltage adjustment d/a converter 35h o o o ? c r13, r14 ?????? use prohibited (not used) ????? ? r15 001111 command reset 00h o o ?? c r16 to r23 ?????? use prohibited (not used) ????? ? r24 011000 dc/dc operation setting 00hoooo c r25 011001 dc/dc step setting 16hoooo c r26 011010 dc/dc oscillation setting 15hoooo c r27 011011 regulator output setting 2ahoooo c r28 011100 lpm setting 00hoooo c r29 to r32 ?????? use prohibited (not used) ????? ? r33 100001dc/dc rise setting 00h oooo c r34, r35 ?????? use prohibited (not used) ????? ? remarks 1. o: enabled, -: disabled, ? 1: only bit 3 disabled, ? 2: only bit 7 enabled 2. the internal set timing is the timing at which the command is enabled. c: enabled when command is set f: enabled at beginning of frame l: enabled at beginning of line notes 1. bit 0 is enabled when line is set. bit 3 is enabled when frame is set. al other bits are enabled when command is set. 2. bits 4 and 5 are enabled when hard reset is performed. all other bits are disabled.
preliminary product information s16269ej2v0pm 16 pd161831 table 4 ? ? ? ? 2. command register list (2/2) d5 to d0 timing generator function reset register no. d5 d4 d3 d2 d1 d0 register name default value use not used command hard internal set timing r36 100100rsw_o start timing setting 0fh o ? o ? c r37 100101rsw_o end timing setting 1dh o ? o ? c r38 100110gsw_o start timing setting 1eh o ? o ? c r39 100111gsw_o end timing setting 2ch o ? o ? c r40 101000bsw_o start timing setting 2dh o ? o ? c r41 101001bsw_o end timing setting 3bh o ? o ? c r42 101010ext1_o start timing setting 0ah o ? o ? c r43 101011ext1_o end timing setting 0ah o ? o ? c r44 101100ext2_o start timing setting 0ah o ? o ? c r45 101101ext2_o end timing setting 0ah o ? o ? c r46 101110ext3_o start timing setting 0ah o ? o ? c r47 101111ext3_o end timing setting 0ah o ? o ? c r48 110000ext1 to ext3 function setting 80h o ? 2o ? c r49 110001goe1 start timing setting 04h o ? o ? c r50 110010goe1 end timing setting 38h o ? o ? c r51 110011dummy line setting 00h o ? o ? f r52, r53 ?????? use prohibited (not used) ????? ? r54 110110com2, vclamp control 00h oooo c r55 110111test m ode setting 00h o o o ? c r56 to r255 ?????? use prohibited (not used) ????? ? remarks 1. o: enabled, -: disabled, ? 1: only bit 3 disabled, ? 2: only bit 7 enabled 2. the internal set timing is the timing at which the command is enabled. c: enabled when command is set f: enabled at beginning of frame l: enabled at beginning of line notes 1. bit 0 is enabled when line is set. bit 3 is enabled when frame is set. al other bits are enabled when command is set. 2. bits 4 and 5 are enabled when hard reset is performed. all other bits are disabled.
preliminary product information s16269ej2v0pm 17 pd161831 4.2.2 65,536/262,144 color select register this register is used to select the number of colors (65,536 or 262,144 colors) of one pixel and specify the data transfer mode when 262,144 colors are selected. if transferring 262,144 colors twice is selected, the time required to transfer the data of one pixel is two times longer than that of the first transfer (if the dot clock frequency is the same). to make the frame frequency for the first transfer and the second transfer the same, therefore, increase the dot clock frequency for the second transfer to twice that of the first transfer. note also that the setting of this register is reflected from the operation of the next frame after the register is set. table 4 ? ? ? ? 3. 65,536/262,144 color select register (r0) register set value function 00h 65,536 colors: 16-bit data is transferred once 01h note 262,144 colors: 12-bit and 6-bit data are transferred twice. 02h note 262,144 colors: 9-bit and 9-bit data are transferred twice. 03h 262,144 colors: 18-bit data is transferred once 04h-ffh use prohibited note the 65,536/262,144 color select register cannot be used in mode that do not use the timing generator. the relationship between each data transfer mode and the display data input pins (d 05 to d 00 , d 15 to d 10 , and d 25 to d 20 ) is shown in the table below. the data input to d 05 to d 00 is output during the period while bsw_o is active, and the data input to d 25 to d 20 is output during the period while rsw_o is active. however, red5 , green5 , blue5 in table 4 ? 4 are the data lines needed to input in 8-color mode. table 4 ? ? ? ? 4. relationship between data transfer mode and display data input pins (? ? ? ? ? ? indicates that input data is invalid) 262,144 colors two transfers, 12-bit + 6-bit two transfers, 9-bit + 9-bit display data input pin 65,536 colors one transfer, 18-bit first transfer second transfer first transfer second transfer d 25 red5 red5 red5 blue5 red5 green2 d 24 red4 red4 red4 blue4 red4 green1 d 23 red3 red3 red3 blue3 red3 green0 d 22 red2 red2 red2 blue2 red2 blue5 d 21 red1 red1 red1 blue1 red1 blue4 d 20 ? note red0 ?? ? ? d 15 green5 green5 red0 blue0 red0 blue3 d 14 green4 green4 ?? green5 blue2 d 13 green3 green3 ?? green4 blue1 d 12 green2 green2 green5 ? green3 blue0 d 11 green1 green1 green4 ?? ? d 10 green0 green0 green3 ?? ? d 05 blue5 blue5 green2 ?? ? d 04 blue4 blue4 green1 ?? ? d 03 blue3 blue3 green0 ?? ? d 02 blue2 blue2 ?? ? ? d 01 blue1 blue1 ?? ? ? d 00 ? note blue0 ?? ? ? note it is not necessary to input data to the d 20 and d 00 pins when 65,536 colors are selected, but amplifier output is performed on the assumption that data input to d 25 and d 05 is input to d 20 and d 00 .
preliminary product information s16269ej2v0pm 18 pd161831 4.2.3 horizontal period valid input start timing setting register this register sets the timing to start inputting the valid data of the horizontal period in hsync and vsync mode. it sets the number of dot clocks from the falling edge of the hsync signal until the input data becomes valid. if transferring display data twice is selected, set half the number of dot clocks actually needed. note also that the setting of this register is reflected from the operation of the next frame after the register is set. table 4 ? ? ? ? 5. horizontal period valid input start timing setting register (r1) register set value number of dot clocks 00h 4 clocks 01h 4 clocks :: 04h 4 clocks 05h 5 clocks 06h 6 clocks 07h 7 clocks :: fdh 253 clocks feh 254 clocks ffh 255 clocks 4.2.4 vertical period valid input start timing setting register this register sets the timing to start inputting the valid data of the vertical period in hsync and vsync mode. it sets the number of hsync from the falling edge of the vsync signal until the input data becomes valid. note also that the setting of this register is reflected from the operation of the next frame after the register is set. table 4 ? ? ? ? 6. vertical period valid input start timing setting register (r2) register set value number of hsync signals 00h 2 01h 2 02h 2 03h 3 04h 4 05h 5 06h 6 :: fdh 253 feh 254 ffh 255
preliminary product information s16269ej2v0pm 19 pd161831 4.2.5 horizontal valid pixel data register this register sets the number of valid pixel data during the horizontal period in hsync and vsync mode. note also that the setting of this register is reflected from the operation of the next frame after the register is set. table 4 ? ? ? ? 7. horizontal valid pixel data register (r3) register set value number of valid data 00h 240 01h 244 02h 480 03h 488 4.2.6 standby register this register is used to set or restore from a standby mode. the data set to bits 7 to 1 of this register is ignored. when a standby command is input, the pd161831 performs white display (source output, and v ss level output by comc) from the next frame following command output. following the execution of this command, execute the regulator off command and the dc/dc converter off for the power supply function. also when standby is canceled, doing the opposite of when standby is input, execute the normal operation command (r4 = ?0?) after setting both the dc/dc converter and the regulator to on.. table 4 ? ? ? ? 8. standby register (r4) bit 0 set value mode 0 normal operation mode 1 standby mode 4.2.7 8-color mode register this register is used to select the 8-color mode. the data set to bits 7 to 1 of this register is ignored. the data line that must be input in 8-color mode differs depending on the selection of the 65,000-color mode and 260,000-color transfer mode. for the actual data line to be used, refer to table 4 ? 4. note that the setting of this register is reflected from the operation of the next line after the register is set. table 4 ? ? ? ? 9. 8-color mode register (r5) bit 0 set value mode 0 65,000/260,000 colors (r0 register is valid) 1 8-color mode
preliminary product information s16269ej2v0pm 20 pd161831 4.2.8 setting register this register is used to set the low power mode and the direction of scanning. data set to bits 6 and bit7 of these register are ignored. table 4 ? ? ? ? 10. setting register (r6) bit name mode bit 0 adjusts the driver bias current of the pd161831 to enter the low power mode. since the through rate of the operational amplifier inside the ic changes, be sure to carefully perform panel evaluation. note that the setting of this bit is reflected from the operation of the next line after the register values are set. bit 0 = 0: driver output low power mode bit 0 = 1: normal mode bit 1 selects the scanning direction by using the grl_o and gstb_o pins. this bit becomes valid as soon as it is set. therefore, it must be set after gate scanning of one frame has been completed and before scanning of the next frame is started. the setting of this bit is reflected in the operation immediately after the register is set. bit 1 = 0: reverse scan (scanning from bottom to top, grl_o = l output) bit 1 = 1: forward scan (scanning from top to bottom, grl_o = h output) bit 2 selects whether the display data input to the pd161831 is input from s 3 to s 242 , or vice versa. <240 output selection> bit2 = 0: s 242 s 3 bit2 = 1: s 3 s 242 <244 output selection> bit2 = 0: s 244 s 1 bit2 = 1: s 1 s 244 the relationship between the input data and output pin is as follows: the setting of this bit is reflected in the operation immediately after the register is set. bit 3 selects whether the line or frame is inverted. in the 8-color mode, the power consumption can be further reduced by selecting frame inversion. the setting of this bit is reflected from the operation of the next line after the register is set. bit 3 = 0: line inversion bit 3 = 1: frame inversion bit 4 performs goe1 output control. when bit 4 = 0, a low level is forcibly output to goe1. bit 4 = 0: forcible output of low level to goe1. bit 4 = 1: normal operation bit 5 controls on/off switching of square wave output from the comc pin. bit 5 = 0: output v ss level bit 5 = 1: output square wave bit 6, bit 7 use prohibited
preliminary product information s16269ej2v0pm 21 pd161831 4.2.9 amplifier drive period setting register in the pd161831, the amplifier drive period is set with the horizontal period address count (hcnt) as the driver output. the amplifier drive period set with this register is the drive period of r, g, and b, respectively, when division by 3 is performed. the amplifier drive start timing is the rgw_o, gsw_o, and bsw_o signal start timing. for detail, refer to figures 4 ? 2 through 4 ? 6. note that the setting of this register is reflected to the operation immediately after the register is set. the effective bits of this register are bit 0 to bit 4. figure 4 ? 7 indicates how the amplifier of the pd161831 is driven. table 4 ? ? ? ? 11. amplifier drive period setting register (r8) register set value horizontal period address count 00h 0 01h 1 02h 2 03h 3 04h 4 :: 1dh 29 1eh 30 1fh 31
preliminary product information s16269ej2v0pm 22 pd161831 figure 4 ? ? ? ? 2. horizontal period amplifier drive timing and gck/goe1 signal output timing (when line inversion is set: when vsync signal is active) pd161831 display timing chart vsync (width = 1h) line hsync vsync clk hcnt gclk_o gstb_o goe1_o goe2_o rsw_o gsw_o bsw_o ext1_o ext2_o ext3_o y1 to y240 comc gn out gn+1 out 30 31 32 33 26 27 28 29 22 23 24 25 18 19 20 21 14 15 16 17 10 11 12 13 6789 2345 -- 01 -- -- 56 57 58 59 52 53 54 55 48 49 50 51 44 45 46 47 40 41 42 43 36 37 38 39 32 33 34 35 28 29 30 31 24 25 26 27 20 21 22 23 56 57 58 59 ------ 012345678910111213 1819 14 15 16 17 gost [5:0] goed [5:0] rst [5:0] red [5:0] gst [5:0] ged [5:0] bst [5:0] bed [5:0] a setup which does not generate a pulse is prohibited about goe1 (prohibition of this address value setup about a start and a stop). it is a timing chart at the time of using level period effective data input start timing as a 16-dot clock by r1 register. the address count of a level period starts after level effective data input start timing. over 1.0 s min. hi-z r output g out p ut b out p ut hi-z r output display clk address value (hcnt) is four times cycling in dotclk display clk address value (hcnt) can be set up to 1-58 (0, 59, and 59 or more addresses prohibited). when all 240 or more clk are put in 1h period, it is added after display clk address value (hcnt) 58 address. r8 a mplifier driving period resistance direct driving period resistance direct driving period r8 amplifier driving period resistance direct driving period r8 amplifier driving period e1st [5:0] e1ed [5:0] e2st [5:0] e2ed [5:0] e1st [5:0] e1ed [5 : 0]
preliminary product information s16269ej2v0pm 23 pd161831 figure 4 ? ? ? ? 3. horizontal period amplifier drive timing and gck/goe1 signal output timing (when line inversion is set: line immediately after vsync to valid data input start line) pd161831 display timing chart line right after vsync to valid data input start ling hsync vsync clk hcnt gclk_o gstb_o goe1_o goe2_o rsw_o gsw_o bsw_o ext1_o ext2_o ext3_o y1 to y240 comc gn out gn+1 out 36 22 27 28 32 30 31 26 34 41 44 38 40 - 3 42 515 67 10 911 8 56 59 58 57 2 1 034 21 16 17 18 19 12 13 14 50 46 20 37 43 23 24 25 29 39 56 12 33 51 52 47 48 49 35 13 10 911 56 57 58 4 59 0 32 54 28 29 30 31 17 18 23 21 24 25 26 27 45 2 1 - 53 54 19 20 22 7 8 15 16 55 14 01 ?? ? ?? dotclk hsync clk hcnt 16 clk over 1.0 s min. gost [5:0] goed [5:0] rst [5:0] red [5:0] gst [5:0] ged [5:0] bst [5:0] bed [5:0] it is a timing chart at the time of using level period effective data input start timing as a 16-dot clock by r1 register. the address count of a level p eriod starts after level effective data in p ut start timin g . a setup which does not generate a pulse is prohibited about goe1 (prohibition of this address value setup about a start and a stop). e1st [5:0] e1ed [5:0] e2st [5:0] e2ed [5:0] e1st [5:0] e1ed [5:0] hi-z r output g out p ut b out p ut hi-z r output r8 a mplifier driving period resistance direct driving period resistance direct driving period r8 amplifier driving period resistance direct driving period r8 amplifier driving period
preliminary product information s16269ej2v0pm 24 pd161831 figure 4 ? ? ? ? 4. horizontal period amplifier drive timing and gck/goe1 signal output timing (when line inversion is set: laid data input start line to gstb output line) pd161831 display timing chart valid data input start line and next line (gstb output) hsync vsync clk hcnt gclk_o gstb_o goe1_o goe2_o rsw_o gsw_o bsw_o ext1_o ext2_o ext3_o y1 t o y240 comc gn out gn+1 out 56 57 58 59 ------ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 - - 3 --- 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 32 33 28 29 30 31 - 012 valid data in p ut start line gstb output over 1.0 s min. a setup which does not generate a pulse is prohibited about goe1 (prohibition of this address value setup about a start and a stop). gost [5:0] goed [5:0] rst [ 5: 0] red [ 5: 0] gst [ 5: 0] ged [5:0] bst [5:0] bed [5: 0] it is a timing chart at the time of using level period effective data input start timing as a 16-dot clock by r1 register. the address count of a level period starts after level effective data input start timin g . e1st [ 5: 0] e1ed [5: 0] e2st [ 5: 0] e2ed [ 5:0 ] e1st [ 5: 0] e1ed [5: 0] r8 a mplifier driving period resistance direct driving period resistance direct driving period r8 amplifier driving period resistance direct driving period r8 amplifier driving period hi - z r output g out p ut b output hi - z r output g
preliminary product information s16269ej2v0pm 25 pd161831 figure 4 ? ? ? ? 5. horizontal period amplifier drive timing and gck/goe1 signal output timing (when frame inversion is set, positive polarity) pd161831 displa y timin g chart ( frame inversion/positive polarit y , 240 output ) hsync vsync clk hcnt gclk_o gstb_o goe1_o goe2 _ o rsw_o gsw_o bsw_o ext1_o ext2_o ext3_o y1 to y240 comc gn out gn+1 out 0 - 1 - 0 29 30 31 28 - - 21 20 18 19 27 10 15 16 11 13 14 32 17 31 23 28 24 25 29 30 41 2 1 4 3 - 32 48 18 19 20 21 26 22 57 58 - 59 - 33 33 34 40 38 35 36 37 39 12 6789 -5 56 49 55 50 51 52 53 54 47 42 43 45 46 44 27 26 23 24 25 10 12 715 811 22 13 14 16 17 56 57 -- 58 59 59 -- 34 26 display clk address value (hcnt) is four times cycling in dotclk display clk address value (hcnt) can be set up to 1-58 (0, 59, and 59 or more addresses prohibited). when all 240 or more clk are put in 1h period, it is added after display clk address value (hcnt) 58 over 1.0 s min. gost [5:0] goed [5:0] a setup which does not generate a pulse is prohibited about goe1 (prohibition of this address value setu p about a start and a sto p) . rst [5:0] red [5:0] gst [5:0] ged [5:0] bst [5:0] bed [5:0] it is a timing chart at the time of using level period effective data input start timing as a 16-dot clock by r1 register. the address count of a level p eriod starts after level effective data in p ut start timin g . e1st [5:0] e1ed [ 5:0 ] e2st [5:0] e2ed [ 5:0 ] e1st [5:0] e1ed [ 5:0 ] r8 a mplifier driving period resistance direct dri vi ng period resistance direct driving period r8 amplifier driving period resistance direct driving period r8 amplifier driving period hi -z r output g out p ut b output hi -z r output
preliminary product information s16269ej2v0pm 26 pd161831 figure 4 ? ? ? ? 6. horizontal period amplifier drive timing and gck/goe1 signal output timing (when frame inversion is set, negative polarity) pd161831 dis p la y timin g chart ( frame inversion/ne g atibe p olarit y , 240 out p ut ) hsync vsync c lk hcnt gc lk_ o gstb_o go e1_ o go e2_ o r s w_ o gs w_ o b s w_ o ext1 _ o ext2 _ o ext3 _ o y1 to y240 comc g n out g n+1 o ut 56 57 58 59 --- 6 2345 - 11 12 10 7 8 9 131415161718192021222324252627282930313233343536373839404142434445464748 52535455 2 3 4 1 567891011121314151617181920212223242526272829303132 33 - 0 - 49 50 58 51 - 1 - 59 - - - 56 57 - 0 over 1.0 a mplifier driving period resistance direct driving period resistance direct driving period r8 amplifier driving period resistance direct driving period r8 amplifier driving period hi -z r output g out p ut b out p ut hi -z r output
preliminary product information s16269ej2v0pm 27 pd161831 the lcd driver circuit of the pd161831 consists of ? resistor?, ? select switch?, ?d/a converter?, and ?output stage?, as shown below. the following amplifier drive period can be selected by using r8, the amplifier drive period setting register. resistor : string resistor for curve select switch: selects curve during positive pole or negative pole driving d/a converter : selects the output voltage level from display data. output stage : consists of a driving amplifier, a switch for voltage hold driving, and an inverter for 8-color display. figure 4 ? ? ? ? 7. output circuit image of amplifier drive operation selction sw dac sw v 0 v 4 amp. out output for 8-color display negative polarity positive polarity
preliminary product information s16269ej2v0pm 28 pd161831 4.2.10 quarter data function register the quarter data function is selected with the bit 0 setting. table 4 ? ? ? ? 12. quarter data function register (r9) bit 0 mode 0 normal operation 1 quarter data function operation when the quarter data function is selected, one pixel of input data is also used as the neighboring 1 pixel of data. the data that is next input externally becomes the pixel data after the neighboring 1-pixel data mentioned above. figure 4 ? ? ? ? 8. quarter data function s1 s2 s3 s4 s5 first input pixel data second input pixel data third input pixel data driver output driver output driver output driver output driver output s1 s2 s3 s4 s5 driver output driver output driver output driver output driver output first input pixel data second input pixel data third input pixel data fourth input pixel data fifth input pixel data
preliminary product information s16269ej2v0pm 29 pd161831 moreover, when the quarter data function is selected, 2-lines? worth of data output are gate scanned during the horizontal period corresponding to 1 line. figure 4 ? ? ? ? 9. gate scan operation when quarter data function is selected hsync gate scan hsync gate scan normal operation mode (gate scan performed once during 1 horizontal period) quarter data function mode (gate scan performed twice during 1 horizontal period) the horizontal period timing is as follows.
preliminary product information s16269ej2v0pm 30 pd161831 figure 4 ? ? ? ? 10. horizontal period timing chart when quarter data function is selected pd161831 displa y timin g chart ( line inversion, 240 output, quarter data function ) hsync v s yn c d o t c lk hcnt gc lk_ o gs tb_ o goe1 _ o goe2 _ o rsw _ o gsw _ o bsw _ o ext1 _ o ext2 _ o ext3 _ o y1 to y240 co m c g n o ut g n+ 1 o ut 27 --- 19 20 21 - -- 10 924 22 25 7 - 8 -- 3 56 57 -- 58 59 6 16 17 18 13 14 11 12 15 42 43 37 28 29 30 31 38 59 56 57 58 11 12 0 47 -- - -- 117182127 22 19 49 50 55 51 52 53 16 526 6 4 78910 20 13 14 15 23 24 25 -- 23 1 35 36 33 34 32 54 48 23 26 39 41 44 40 45 46 5 04 2 i t is a timing chart at the time of using l evel period effective data input start ti ming as a 16-dot clock by r1 register. the address count of a level period starts after l evel effective data i nput start ti ming. after hsync becomes active, a level period starts by 1 clock of dotclk. after hsync becomes active, gclk becomes active by 2 clock of dotclk. di spl ay clk address val ue ( hcnt) i s f our t i mes cycl i ng i n dotclk di spl ay clk addr ess val ue (hcnt) can be set up t o 1- 58 (0, 59, and 59 or more addresses prohi bi t ed). when al l 240 or mor e clk are put i n 1h peri od, i t i s added af t er di spl ay clk address val ue ( hcnt) 58 addr ess. over 1.0 s min. gost [5:0] goed [5:0] over 1.0 ms min . rst [5:0] red [5:0] gst [5:0] ged [5:0] bst [5:0] bed [5:0] e1st [5:0] e1ed [ 5:0 ] e2st [5:0] e2ed [ 5:0] e1st [5:0] e1ed [ 5:0] a setup which does not generate a pulse is prohibited about goe1 (prohibition of this address value setup about a start and a stop). it is a timing chart at the time of using level period effective data input start timing as a 16-dot clock by r1 re g ister. the address count of a level p eriod starts after level effective data in p ut start timin g . r8 a mplifier driving period resistance direct dri vi ng period resistance direct driving period r8 amplifier driving period resistance direct driving period r8 amplifier driving period hi -z r output g out p ut b output hi -z r output
preliminary product information s16269ej2v0pm 31 pd161831 as an image, in order to perform display of 240 outputs x 320 lines during normal operation, 240 outputs x 640 lines of data are input, but when the quarter data function is selected, in order to perform display of 240 outputs x 320 lines, just 120 outputs x 160 lines of data can be input. while display is less fine compared to during normal operation, the input data is just one fourth the amount during normal operation, and transfer data can be reduced during moving picture display. amount of data required to display 1 screen = 240 outputs x 320 lines amount of data required to display 1 screen = 120 outputs x 160 lines panel size 240 outputs x 320 lines 4.2.11 level shifter voltage setting register then negative voltage level of the level shifter is set by setting bit 0 and bit1. the circuit block of the level shifter is divided into the gate control signal side (gclk_o, gstb_o, goe1_o, goe2_o) and the driver output related signal side (rsw_o, gsw_o, bsw_o, ext1_o to ext3_o), and the negative voltage side voltage level can be selected individually for the gate control signal side and the driver output related signal side between either v ss1 and v ss2 with the r11 register. the data set to bit 1 and bit 2 is ignored. note that the setting of this register is reflected to the operation immediately after the register is set. table 4 ? ? ? ? 13. level shifter voltage setting register (r10) bit name mode bit 0 sets the voltage level on the negative voltage side of the gate output control signals (gclk_o, gstb_o, goe1_o, goe2_o). bit 0 = 0: v ss2 level bit 0 = 1: v ss1 level bit 1 sets the voltage level on the negative voltage side of the driver output related signals (rsw_o, gsw_o, bsw_o, ext1_o to ext3_o) bit 1 = 0: v ss2 level bit 1 = 1: v ss1 level
preliminary product information s16269ej2v0pm 32 pd161831 4.2.12 common amplitude voltage adjustment d/a converter register the common amplitude voltage can be selected by setting bit 0 to bit 3 of the r11 register. the voltage between (34/50)*v s and (49/50)*v s is divided by the 4-bit d/a converter. note that the setting of this register is reflected to the operation immediately after the register is set. 4.2.13 common center voltage adjustment d/a converter register the common center voltage can be selected by setting bit 0 to bit 6 of the r12 register. the voltage between 0 (v) and 0.6*v s (v) is divided by the 7-bit d/a converter. note that the setting of this register is reflected to the operation immediately after the register is set. 4.2.14 command reset register bit 0 of this register is used to initialize the command register. data set to bit 1 to bit 7 is ignored. command reset is automatically cleared after it is set. the setting of this bit is reflected in the operation immediately after the register is set. table 4 ? ? ? ? 14. command reset register (r15) bit 0 mode 0 normal operation 1 command reset 4.2.15 dc/dc operation setting register the register is used to switch on/off the dc/dc converter controls and switch on/off boosting of each power supply. table 4 ? ? ? ? 15. dc/dc operation setting register (r24) bit name mode bit 0 controls on/off in dc/dc converter. bit 0 = 0: dc/dc converter off bit 0 = 1: dc/dc converter on bit 1 use prohibited bit 2 control on/off in v dd2 booster. bit 2 = 0: v dd2 booster off bit 2 = 1: v dd2 booster on bit 3 control on/off in v dc2 booster. bit 3 = 0: v dc2 booster off bit 3 = 1: v dc2 booster on bit 4 control on/off in v ss1 booster. bit 4 = 0: v ss1 booster off bit 4 = 1: v ss1 booster on bit 5 control on/off in v ss2 booster. bit 5 = 0: v ss2 booster off bit 5 = 1: v ss2 booster on bit 6 control on/off in v r regulator. bit 6 = 0: v r regulator off bit 6 = 1: v r regulator on bit 7 use prohibited
preliminary product information s16269ej2v0pm 33 pd161831 4.2.16 dc/dc step setting register this register is used to set the boost step, etc., of the dc/dc converter. table 4 ? ? ? ? 16. dc/dc step setting register (r25) bit name mode bit 0: v cd2 selects the number of boost steps for v dc2. v cd2 = 0: v dc2 = v dc x 2 v cd2 = 1: v dc2 = v dc x 3 bit 1: vm s selects the boost mode for v dc2 . vm s = 0: single boosting mode vm s = 1: dual boosting mode bit 2: vrsel0 bit 3: vrsel1 bit 4: vrsel2 selects the v r regulator?s output voltage. : v r = 3.0 v : v r = 3.5 v : v r = 4.0 v : v r = 4.5 v : v r = 4.75 v : v r = 5.0 v : v r = 5.25 v : v r = 5.5 v bit 5 to bit7 use prohibited 4.2.17 dc/dc oscillation setting register this register is used to set the boost frequency, etc., of the dc/dc converter. table 4 ? ? ? ? 17. dc/dc oscillation setting register (r26) bit name mode bit 0: fs0 bit 1: fs1 selects the v dc2 boost frequency when other an the power supply function low-power mode is selected. : f osc /2, : f osc /4 : f osc /8, : f osc /16 bit 2: fs2 bit 3: fs3 selects the v dd2 , v ss1 , v ss2 boost frequency when other than the low-power supply function power mode is selected. : f osc /2, : f osc /4 : f osc /8, : f osc /16 bit 4: cls0 bit 5: cls1 bit 6: cls2 selects the internal oscillation frequency of the dc/dc converter function. : f osc = 12.5 khz, dcclk: open : f osc = 15 khz, dcclk: open : f osc = 20 khz, dcclk: open : external clock dcclk input mode : external clock dck 128 cycle mode : external clock dck 256 cycle mode selects the internal oscillation frequency of the dc/dc converter function. internal oscillation external dck 128 cycles external dck 256 cycles fup = 0 f osc dck/128 dck/256 fup = 1 f osc x 2 dck/64 dck/128 bit 7: fup
preliminary product information s16269ej2v0pm 34 pd161831 4.2.18 regulator output setting register this register is used to switch the regulator on/off, set the output voltage, etc. table 4 ? ? ? ? 18. regulator output setting register (r27) bit name mode bit 0: rgon controls v s regulator on/off. rgon = 0: v s regulator off rgon = 1: v s regulator on bit 1: vsel0 bit 2: vsel1 bit 3: vsel2 selects the v s regulator output voltage. : v s = 3.0 v : v s = 3.5 v : v s = 4.0 v : v s = 4.5 v : v s = 4.75 v : v s = 5.0 v : v s = 5.25 v : v s = 5.5 v bit 4: exrv selects whether to use an external resistor for the v s regulator. exrv = 0: internal resistor mode exrv = 1: connect external resistor to mv s and set voltage to any desired value. bit 5: acs0 bit 6: acs1 selects the v r and v s amplifier current. : amp. current = 5 a : amp. current = 10 a : amp. current = 15 a : amp. current = 30 a bit 7 use prohibited
preliminary product information s16269ej2v0pm 35 pd161831 4.2.19 power supply function lpm setting register this register is used to set the power supply function low-power mode, etc. table 4 ? ? ? ? 19. power supply function lpm setting register (r28) bit name mode bit 0: lpm controls the power supply function low-power mode lpm = 0: normal mode lpm = 1: low power mode bit 1: lfs0 bit 2: lfs1 selects the v dc2 boost frequency when the power supply function low- power mode is selected. : f osc /8, : f osc /16 : f osc /32, : f osc /64 bit 3: lfs2 bit 4: lfs3 selects the v dd2 , v ss1 , and v ss2 boost frequency when the power supply function low-power mode is selected. : f osc /8, : f osc /16 : f osc /32, : f osc /64 bit 5: lacs0 bit 6: lacs1 selects the v r and v s amplifier current. : amp. current = 1.25 a : amp. current = 2.5 a : amp. current = 5.0 a : amp. current = 7.5 a bit 7 use prohibited
preliminary product information s16269ej2v0pm 36 pd161831 4.2.20 dc/dc startup setting register this register is used to set the dc/dc startup time, startup mode, etc. table 4 ? ? ? ? 20. dc/dc startup setting register (r33) bit name mode bit 0: pupt0 bit 1: pupt1 sets the v dc2 , v dd2 , v ss1 , and v ss2 on time at dc/dc startup. this bit is effective only when ponm = 1. for the startup time, refer to table 4 ? 21. bit 2: dupf0 bit 3: dupf1 sets the dc/dc operating frequency at dc/dc startup. this bit is effective only when bit 5 (ponm) = 0 and bit 4 (pon) = 1 are set. : f osc /8, : f osc /16 : f osc /32, : f osc /64 bit 4: pon selects the operating frequency at v dc2 , v dd2 , v ss1 , and v ss2 rise at startup. ponm = 0 is only valid. pon = 0: normal operation pon = 1: rising operation bit 5: ponm selects the dc/dc startup operation?s internal sequence and external sequence. ponm = 0: external sequence ponm = 1: internal sequence bit 6, bit7 use prohibited table 4 ? ? ? ? 21. dc/dc rising time selection ponm pon pupt0 pupt1 vdc2on rgonr vs1/2on vd2on remark 1 x 0 0 16/f osc 2048/f osc 1.5 x 2048/f osc 2.5 x 2048/f osc use internal sequence 1 x 1 0 16/f osc 256/f osc 1.5x 256/f osc 2.5x 256/f osc use internal sequence 1 x 0 1 16/f osc 512/f osc 1.5 x 512/f osc 2.5 x 512/f osc use internal sequence 1 x 1 1 16/f osc 1024/f osc 1.5 x 1024/f osc 2.5 x 1024/f osc use internal sequence 0 1 x x external input external input external input external input use external sequence 00xx normal mode remark x: 0 or 1 4.2.21 driver output related control signal registers (r36 to r47) these registers set the start timing and the end timing of the active period of the rsw_o, gsw_o, bsw_o, ext1_o to ext3_o signals, with the clock obtained by dividing a 1-line horizontal period by 4 as the reference (reference clock of 60 clocks in the case of 1 line consisting of 240 pixels of data). the effective bits of these registers are bit 0 to bit 5, respectively. (values up to 01h to 3bh can be set.)
preliminary product information s16269ej2v0pm 37 pd161831 4.2.22 ext1 to ext3 function setting register ext1_o outputs each line signal at the timing set with r42 and r43, but for extr2_o and ext3_o, the output cycle can be selected depending on the positive polarity and negative polarity of the common. table 4 ? 22 shows the concrete details. moreover, the rsw_o, bsw_o, gsw_o inverted signals can be selected for ext1_o to ext3_o. table 4 ? ? ? ? 22. ext1 to ext3 function setting register (r48) bit name mode bit 0 sets the ext2_o output during line inversion. bit 0 = 0: outputs every line bit 0 = 1: outputs only line when common is positive. bit 1 sets the ext2_o output during frame inversion. bit 1 = 0: outputs every line bit 1 = 1: outputs only the first display line for frames when the common is positive. bit 2 sets the ext3_o output during line inversion. bit 2 = 0: output every line bit 2 = 1: output only lines when the common is negative. bit 3 sets the ext3_o output during frame inversion. bit 3 = 0: output every line bit 3 = 1: outputs only the first display line for frames when the common is negative. bit 4 to bit 6 use prohibited bit 7 selects the mode for outputting the rsw_o, gsw_o, and bsw_o inverted signals from ext1_o to ext3_o. bit 7 = 0: executes the operation set to bit 0 to bit 3. bit 7 = 1: outputs the rsw_o, gsw_o, and bsw_o inverted signals from ext1_o to ext3_o. ext1_o = /rsw_o, ext2_o = /gsw_o, ext3_o = /bsw_o 4.2.23 goe1 signal setting registers (r49, r50) these registers set the start timing (r49) and the end timing (r50) of the active period of the goe1_o signal, with the clock obtained by dividing the 1-line horizontal period by 4 as the reference (reference clock of 60 clocks in the case of 1 line consisting of 240 pixels of data). 4.2.24 dummy line setting register (r51) this register is used to set whether to perform dummy output to the first line of a frame. in the case of a dummy line, the data input in the immediately preceding line is output. refer to figure 4 ? 11 and figure 4 ? 12. table 4 ? ? ? ? 23. dummy line setting register (r51) bit 0 mode 0 dummy line 1 no dummy line
preliminary product information s16269ej2v0pm 38 pd161831 figure 4 ? ? ? ? 11. vertical period gstb (top: no dummy line, bottom: dummy line) pd161831 display timing chart 1) no dummy lin e hsync vsync gclk _ o gstb _ o goe1 _ o rsw _ o gsw _ o bsw _ o comc 2) dummy line hsync vsync gclk _ o gstb _ o goe1 _ o rsw _ o gsw _ o bsw _ o comc valid data input start line gstb output gstb output valid data input start line
preliminary product information s16269ej2v0pm 39 pd161831 figure 4 ? ? ? ? 12. vertical period gstb (top: no dummy line, bottom: dummy line) pd161831 display timing chart 1) no dummy line hsync vsync gclk _ o gstb _ o goe1 _ o rsw _ o gsw _ o bsw _ o comc 2) dummy line hsync vsync gclk _ o gstb _ o goe1 _ o rsw _ o gsw _ o bsw _ o comc gstb output valid data input start line gstb output valid data input start line
preliminary product information s16269ej2v0pm 40 pd161831 5. timing generator non-use function operation using an external signal without using the on-chip timing generator function is possible by setting the tcon pin (tcon = h). when the timing generator non-use function is selected, data input is performed using the following pins. the concrete timing chart is shown on the following. ? dck: dot clock ? d 00 to d 05 , d 10 to d 15 , d 20 to d 25 : data bus ? sthr, sthl: data input start pulse ? stb: data latch input ? ap: amplifier drive period control ? pol: polarity inversion signal however, the serial interface can be used, and the common and power supply settings performed with the serial interface. moreover, when the timing generator non-use function is selected, instead of generating signals through the on-chip timing generator for gclk_o, gstb_o, goe1_o, goe2_o, rsw_o, gsw_o, bsw_o, and ext1_o to ext3_o signals, the signals input from the gclk_i, gstb_i, goe1_i, goe2_i, rsw_i, gsw_i, bsw_i, and ext1_i to ext3_i are output via a level shifter. the signals input to rsw_i, gsw_i, and bsw_i are also used as the amplifier output timing. the level shifter circuit block is divided into the gate control signal side and the driver output related signal side, and it is possible to individually select the negative voltage side voltage level individually from v ss2 and v ss3 at the gate control signal side and the driver output-related signal side. (refer to 4.2.12 common amplitude voltage adjustment d/a converter register.)
preliminary product information s16269ej2v0pm 41 pd161831 figure 5 ? ? ? ? 1. data input timing chart when timing generator non-use function is selected (r6, bit 2 = h) (unless otherwise specified, v ih = 0.7 v dd1 , v il = 0.3 v dd1 ) pw clk(l) clk pol v out stb d 00 to d 05 d 10 to d 15 d 20 to d 25 sthr sthl pw clk(h) t r t setup2 invalid t hold2 123 240 241 t f pw clk t plh1 t setup1 90% 10% t hold1 t stb-sth pw stb t hold4 t setup4 t spl invalid (1st dr.) (1st dr.) t phl1 last data hi-z t ldt rsw_0 gsw_0 bsw_0 t pol-rsw hi-z hi-z hi-z t clk-stb
preliminary product information s16269ej2v0pm 42 pd161831 6. interface 6.1 rgb interface the rgb interface has the following two modes: - hsync, vsync mode each mode is explained below. 6.1.1 hsync, vsync mode this mode is used to input display data from the dck, hsync, vsync, d 05 to d 00 , d 15 to d 10 , and d 25 to d 20 pins. in this mode, the value set to the r3 register is valid as the number of valid data in the horizontal period. figure 6 ? 1 shows the timing chart. input at least 1 dot clock for the front porch period. figure 6 ? ? ? ? 1. timing chart in hsync, vsync mode (when cks = l, hseg = l, vses = l) vsync hsync invalid invalid invalid 1st line last line 1st pixel 2nd pixel last pixel t vb = vertical back porch period t hb = horizontal back porch period 1 line period hsync dck 1 pixel period t vb note t hb note invalid invalid 1st pixel last pixel d 05 to d 00 d 15 to d 10 d 25 to d 20 invalid d 05 to d 00 d 15 to d 10 d 25 to d 20 d 05 to d 00 d 15 to d 10 d 25 to d 20 note
preliminary product information s16269ej2v0pm 43 pd161831 6.2 serial interface the pd161831 uses an 8-bit serial interface to set registers related to the horizontal period and vertical period from the mcu, and control the timing of outputting strobe signals to the gate driver. in addition, the back panel lcd controller driver can also be controlled. 6.2.1 serial interface between mcu and pd161831 the serial interface between mcu and pd161831 can acknowledge serial data input (si), serial clock input (sclk), and serial data output (so) if the chip select signal (lcdcs) is active (lcds = h). this interface supports spi, and its relationship with the valid edge of the serial clock and the active level of the serial clock can be set by using the scleg0 and scleg1 pins. table 6 ? ? ? ? 1. relationship between serial clock and data pin name scleg1 scleg0 active level of serial clock input timing of serial data output timing of serial data l l low level rising edge of serial clock falling edge of serial clock l h low level falling edge of serial clock rising edge of serial clock h l high level falling edge of serial clock rising edge of serial clock h h high level rising edge of serial clock falling edge of serial clock figure 6 ? 2 shows the signal chart of the serial interface. figure 6 ? ? ? ? 2. serial interface signal chart a7 a6 a5 a4 a3 a2 a1 a0 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d7 d6 d5 d5 d4 d3 d1 d2 d0 d4 d3 d2 d1 d0 lcdcs sclk (scleg1 = l) so & si (scleg0 = l) so & si (scleg0 = h) sclk (scleg1 = h) serial interface operation specification register transfer command & data transfer remarks 1. ? ? indicates the timing of reading data. 2. if the chip is not active, the shift register and counter are reset to the default status. 3. when wiring scl, the influence of terminal reflection and external noise due to the wiring length must be taken into consideration. it is recommended to confirm the operation on the actual system.
preliminary product information s16269ej2v0pm 44 pd161831 figures 6 ? 3 and 6 ? 4 show the relationship between the read/write operation and the scleg0 and scleg1 pins setting. a read or write operation is specified by a command. when a read operation is specified by a command (a5 bit = 1), the 8-bit data transferred next is read. figure 6 ? 4 gives a specific example. be aware that the so pin becomes hi-z at all times other than when data is output. figure 6 ? ? ? ? 3. serial interface signal chart (write sequence) a7 a6 a5 a4 a3 a2 a1 a0 lcdcs si sclk d7 d6 d5 d4 d3 d2 d1 d0 lcdcs si sclk a7 a6 a5 a4 a3 a2 a1 a0 lcdcs si sclk d7 d6 d5 d4 d3 d2 d1 d0 a7 a6 a5 a4 a3 a2 a1 a0 lcdcs si sclk d7 d6 d5 d4 d3 d2 d1 d0 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 serial interface operation specification transfer - specification of register - specification of read or write - selection of back panel lcd function command & data transfer - selection of command register - transfer of set values of command register serial interface operation specification transfer - specification of register - specification of read or write - selection of back panel lcd function command & data transfer - selection of command register - transfer of set values of command register serial interface operation specification transfer - specification of register - specification of read or write - selection of back panel lcd function command & data transfer - selection of command register - transfer of set values of command register serial interface operation specification transfer - specification of register - specification of read or write - selection of back panel lcd function command & data transfer - selection of command register - transfer of set values of command register
preliminary product information s16269ej2v0pm 45 pd161831 figure 6 ? ? ? ? 4. serial interface signal chart (read sequence) a7 a6 a5 a4 a3 a2 a1 a0 lcdcs si so sclk d7 d6 d5 d4 d3 d2 d1 d0 hi-z hi-z hi-z hi-z a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 hi-z hi-z a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 hi-z hi-z a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 lcdcs si so sclk lcdcs si so sclk lcdcs si so sclk a7 serial interface operation specification register transfer command & data transfer serial interface operation specification register transfer command & data transfer serial interface operation specification register transfer command & data transfer serial interface operation specification register transfer command & data transfer hi-z is entered at lcdcs or the next sclk input. hi-z is entered at lcdcs or the next sclk input.
preliminary product information s16269ej2v0pm 46 pd161831 6.2.2 serial interface between pd161831 and back panel lcd controller driver this 8-bit serial interface is used to control the back panel lcd. when a function to transfer data to the back panel lcd is selected by a command (a6 bit = 1), the chip select signals (/cs1 and cs2) for the back panel lcd are asserted. when data is input from the sclk and si pins to transfer parameters and data, the polarity of the back panel lcd clock (sclk_sub) is the low level (high-level start) and data is output from the back panel serial data output line (so_sub) at the falling edge of the clock, regardless of the polarity and edge specification of the clock input to sclk. bit a0 of the command can be used to specify the level to be output to the a0 pin. if ?command specification? is specified by the a0 bit (a0 bit = 0), the a0 pin outputs a low level when the data of the parameter & data register is transferred. if ?parameter setting? is specified by the a0 bit (a0 bit = 1), the a0 pin outputs a high level when the data of the parameter & data register is transferred. this interface can be used even in the standby mode. the transfer operation is illustrated below. figure 6 ? ? ? ? 5. serial interface signal chart (access to back panel lcd, scleg0 = scleg1 = h) d7 d6 d5 d4 d3 d2 d1 d0 lcdcs sclk_sub sdi so_sub sclk a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 < pd161831 to sub lcd controller driver> /cs1 cs2 a0 serial interface operation specification register transfer command & data transfer transfer to back panel
preliminary product information s16269ej2v0pm 47 pd161831 this interface is effective in the following cases: - when an access to the back panel lcd controller driver is to be (or must be) made by the serial interface. - if the specifications of the internal serial interface of the mcu in the set differ from the specifications of the back panel lcd controller driver. (even if the serial interface of the mcu does not start when the serial clock is high, output data at the falling edge of the clock, and input data at the rising edge of the clock (frequently used specifications), the serial interface of the pd161831 supports spi and any input). an example where the back panel serial interface is necessary is given below. figure 6 ? ? ? ? 6. example where back panel serial interface is necessary pd161831 mcu /cs so sclk /cs1, cs2 so_sub sclk /cs si sclk serial interface this cannot be connected if specifications of serial interface differ. clock data clock data back panel lcd
preliminary product information s16269ej2v0pm 48 pd161831 7. relationship between input data and output voltage value the pd161831 includes a resistor for normally-black support. the relationship between the input data and the output voltage is shown in figure 7 ? 2. any 3 major points v 1 -v 3 from the lcd panel -characteristics curve can be used as the external power supplies. the relation v 0 -v 4 external power supplies and correction resistance is shown in table 7 ? 1, figure 7 ? 1. table 7 ? ? ? ? 1. relationship between external power supplies and correct voltage and resistance pin name voltage (v) resistance ( ? ) v 0 v s t.b.d. v 1 0.7 x v s t.b.d. v 2 0.5 x v s t.b.d. v 3 0.3 x v s t.b.d. v 4 0 t.b.d. figure 7 ? ? ? ? 1. relationship between external power supplies and correction resistance v s v ss t.b.d. ? t.b.d. ? t.b.d. ? t.b.d. ? v s (v) 0.7 x v s 0.5 x v s 0.3 x v s 0 (v) external power supply pins v 0 -v 4 can be customized at any place of the correction voltage. the string resistance between v ss -v s that generates the correction voltage is divided by 250, from which the desired voltage can be selected and the correction voltage can be customized. in addition, positive or negative polarity can also be selected for each correction voltage.
preliminary product information s16269ej2v0pm 49 pd161831 table 7 ? ? ? ? 2. relationship between input data and output voltage value t.b.d.
preliminary product information s16269ej2v0pm 50 pd161831 figure 7 ? ? ? ? 2. relationship between positive/negative polarity and data output t.b.d.
preliminary product information s16269ej2v0pm 51 pd161831 8. connection of correction resistor to power supply and gnd pins connection of the correction resistors of the pd161831, correction resistor power supplies (v 0 -v 4 ) is shown below. depending on the setting of the gam pin, the maximum and minimum potential of the correction resistors can be changed between v s -v ss and v 0 -v 4 . figure 8 ? ? ? ? 1. gam pin function -selection sw v 0 gam gam sw1 sw2 sw1 sw2 sw1 sw2 gam = l gam = h v s v ss v 1 v 2 v 3 v 4 positive polarity negative polarity
preliminary product information s16269ej2v0pm 52 pd161831 9. -correction power supply connection example the pd161831 enables customization of the -correction power supply on both the positive and negative polarity sides (for details, refer to 7. relationship between input data and output voltage value ). consequently, a -correction power supply does not have to be input externally when a single source-driver chip is being used in the panel. figure 9 ? ? ? ? 1. -correction power-supply connection example pd161831 v 0 v 1 v 2 v 3 v 4 open single chip pd161831 v 0 v 1 v 2 v 3 v 4 pd161831 v 0 v 1 v 2 v 3 v 4 pd161831 v 0 v 1 v 2 v 3 v 4 v n - v n short pd161831 v 0 v 1 v 2 v 3 v 4 pd161831 v 0 v 1 v 2 v 3 v 4 multiple chip external power supply input external power supply input
preliminary product information s16269ej2v0pm 53 pd161831 10. reset the pd161831 can be reset by hardware (/reset pin) or a command (r15 register). a hardware reset resets all the functions, including the registers except serial interface. a command reset initializes only the registers. be sure to execute a hardware reset and command reset immediately after power application. each reset is explained below. 10.1 hardware reset when a hardware reset is input (/reset = l), reset is performed for the registers listed in table 4 ? 2 and the on-chip hardware function. (initialization of the serial interface counter is performed from lcdcs.) therefore, even when the timing generator non-use mode is selected, be sure to input a hardware reset. while the hardware reset signal is being input (/reset = l h) and during the period of ?vsync x 20? after bit 0 of the r24 register has been set to 1 (dcon = 1) after the reset was cleared, all the gate outputs are set to off, and the charge on the tft panel pixels is decreased to 0. figure 10 ? 1 shows the timing between when the hardware reset signal is input and when display output is produced. figure 10 ? ? ? ? 1. from input of hardware reset to display output /reset gclk goe1 dcon (r24: bit 0) goe2 command reset a low level is forcibly output for the duration of [vsync x 20] after bit 0 of r24 register is set to 1 (dcon = 1) after /reset is cleared. set each register while goe1 = l when bit 4 of the r4 register = 0, goe1 output continues to be low level even after the ?vsync x 20? period has elapsed after bit 0 of the r24 register is set to 1 (dcon =1). moreover, if bit 4 of the r4 register is set to ?1? before the ?vsync x 20? period elapses after bit 0 of the r24 register has been set to (dcon = 1), low output is performed from the goe1 pin until the ?vsync x 20? time has elapsed. 10.2 command reset a command reset (r15 register) only initializes the registers.
preliminary product information s16269ej2v0pm 54 pd161831 11. goe1 and goe2 signals the output of the goe1 and goe2 signals changes according to the setting of the dcon signal and the input of /reset and standby. -goe1: after dcon is set to 1 (bit 0 of r24 register is set to 1), the goe1 signal outputs a low level for a period of ?vsync x 20?, and output of all the gates is switched off. (all gates are off at power application.) -goe2: in standby mode, when dcon = 0, goe2 outputs a low level and output of all the gates is switched on. (in standby mode, the charge of the panel is discharged.) refer to figure 11 ? 1 below for details. figure 11 ? ? ? ? 1. goe1 and goe2 signal output /reset goe1 after bit 0 of r24 register is set to 1 (dcon = 1), a low level is forcibly output for a period of [20 x vsync] dcon (r24: bit 0) command reset goe2 standby on, commands executed standby off, commands executed power supply cut all gates on all gates off all gates on all gates off all gates on all gates off regarding the goe1 signal, the above-described function does not work when the timing generator function is not used, and output enable/disable for the goe1 signal following reset release can be controlled only with the r6 register. 12. power supply on/off sequence t.b.d.
preliminary product information s16269ej2v0pm 55 pd161831 13. electrical specifications absolute maximum ratings (v ss1 = v ss2 = 0 v) parameter symbol rating unit logic part supply voltage v cc ?0.3 to +4.5 v driver part supply voltage v s ?0.3 to +6.0 v input voltage v i ?0.3 to v cc + 0.3 v output voltage v o ?0.3 to v cc + 0.3 v operating ambient temperature t a ?40 to +85 c storage temperature t stg ?55 to +125 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. recommended operating range (t a = ?40 to +85 c, v ss = 0 v) parameter symbol condition min. typ. max. unit logic part supply voltage v cc 2.2 3.6 v driver part supply voltage v s 4.5 5.0 5.5 v booster reference power supply v dc 2.5 3.6 v high-level input voltage v ih 0.7 v cc v cc v low-level input voltage v il 0 0.3 v cc v -corrected voltage v 0 -v 4 v ss v s v v cc = 2.5 to 5.5 v 20 mhz clock frequency f clk v cc = 2.2 to 5.5 v 16 mhz
preliminary product information s16269ej2v0pm 56 pd161831 electrical characteristics (t a = ?40 to +85 c, v cc = 2.2 to 3.6 v, v s = 5.0 v 0.5 v, v ss = 0 v) parameter symbol condition min. typ. max. unit input leak current i ih 1.0 a i il except testin1, testin2 ? 1.0 a input current i ih2 testin1, testin2 1.5 5.0 a high-level output voltage v oh except comc, i oh = ? 0.1 ma v cc ? 0.5 v low-level output voltage v ol except comc, i ol = +0.1 ma 0.5 v high-level output voltage v oh2 comc, i oh = ? 1.0 ma t.b.d. v low-level output voltage v ol2 comc, i ol =+1.0 ma t.b.d. v -correction power-supply static current consumption i v 0 = 5.0 v, v 4 = 0 v (gam = l) 115 230 460 a i voh1 v s = 5.0 v, v out = v x ? 1.0 v note1 input data: 1fh t.b.d. t.b.d. ma driver output current (amp. drive) i vol1 v s = 5.0 v, v out = v x + 1.0 v note1 input data: 20h t.b.d. t.b.d. ma v oh3 v s = 5.0 v, i o = ? 100 a t.b.d. v driver output voltage (8-color display mode) v ol3 v s = 5.0 v, i o = +100 at.b.d.v output voltage deviation ? v o 10 20 mv output voltage range v o rgb data: 00h to 3fh v ss + 0.05 v s ? 0.05 v comdc output impedance r comdc i o = ? 40 at.b.d. ? v ref input voltage range v refin v v dd1 boost voltage v dd1 i dd1 = +300 a1.7 v s 2.0 v s v v dc2 boost voltage 1 v dc2 v dc2 = l (x2 boost), i dc = + 1.0 ma 1.9 v dc 2.0 v dc v v dc2 boost voltage 2 v dc2 v dc2 = l (x3 boost), i dc = + 1.0 ma 2.8 v dc 3.0 v dc v v ss2 boost voltage v ss2 i ss2 = ? 300 a ? 1.0 v s ? 0.8 v s v v ss3 boost voltage v ss3 i ss3 = ? 300 a ? 3.0 v s ? 2.7 v s v v dd1 output resistance rv dd1 i dd1 = +300 a1.53.05.0k ? v dc2 output resistance 1 rv dc21 v dc2 = l (x2 boost), i dc = + 1.0 ma 50 100 200 ? v dc2 output resistance 2 rv dc22 v dc2 = l (x3 boost), i dc = + 1.0 ma 100 200 400 ? v ss2 output resistance rv ss2 i ss2 = ? 300 a123k ? v ss3 output resistance rv ss3 i ss3 = ? 300 a1.53.05.0k ? v s output voltage v s no load 4.5 5.0 5.5 v v r output voltage v r no load 4.5 5.0 5.5 v v s output resistance rv s v dc2 = 6.0 v, i s = + 1.0 ma, v s = 5.0 v 30 60 ? v r output resistance rv r v dc2 = 6.0 v, i r = + 1.0 ma, v s = 5.0 v t.b.d. t.b.d. ? logic part static current consumption i cc1 no load, standby mode 10 a logic part dynamic current consumption i cc2 no load note2 0.6 0.9 ma driver part static current consumption i dc1 no load, v dc = 2.8 v, standby mode t.b.d. t.b.d. a no load, v dc = 2.8 v, v s = 5.0 v note2 2.6 t.b.d. ma driver part dynamic current consumption i dc2 no load, v dc = 2.8 v, v s = 5.0 v note2 , 8-color mode 1.3 t.b.d. ma notes 1. v x refers to the output voltage of analog output pins s 1 to s 240 . v out refers to the voltage applied to analog output pins s 1 to s 240 . 2. f clk = 15 mhz, stb cycle = 52 s, ap pulse width (each multiplexer switch amplifier driving time) = 10 s, ba = l (low power mode)
preliminary product information s16269ej2v0pm 57 pd161831 switching characteristics (t a = ?40 to +85 c, v cc = 2.2 to 3.6 v, v s = 5.0 v 0.5 v, v ss = 0 v) parameter symbol condition min. typ. max. unit start pulse delay time t plh1 c l = 15 pf 30 ns driver output delay time t plh2h 12 s (high power mode, with load) t phl2h c l = 30 pf, ap v out ? 100 mv, or v out +100 mv 12 s t plh2l 15 s driver output delay time (low power mode, with load) t phl2l c l = 30 pf, ap v out ? 100 mv, or v out +100 mv 15 s high capacitance c i1 v 0 -v 4 , t a = 25 c 5 15 pf c i2 except for v 0 -v 4 ,t a = 25 c1015pf dc/dc oscillation frequency f dcdc fs0 = fs1 = h 10 15 20 khz dcclk input frequency f dcclk 15 50 khz
preliminary product information s16269ej2v0pm 58 pd161831 rgb interface (1/2) vsync hsync invalid invalid invalid 1st line last line 1st pixel 2nd pixel last pixel t vb = vertical back porch period t hb = horizontal back porch period 1 line period hsync dck 1 pixel period t vb note t hb note invalid invalid 1st pixel last pixel d 05 to d 00 d 15 to d 10 d 25 to d 20 invalid d 05 to d 00 d 15 to d 10 d 25 to d 20 d 05 to d 00 d 15 to d 10 d 25 to d 20 note
preliminary product information s16269ej2v0pm 59 pd161831 rgb interface (2/2) t v vsync t vp display period (hsync) pclk data 0.5 v cc 0 175 invalid invalid t vb t vf t vd t h t hp t hb t hf t hd t c t ch t ds t ch (r0 to r4) (g0 to g4) (b0 to b4) 0.5 v cc display period
preliminary product information s16269ej2v0pm 60 pd161831 t a = ?40 to +85 c, v cc = 2.2 to 3.6 v, v s = 5.0 v 0.5 v, v ss = 0 v name symbol min. typ. max. unit remark v cc 2.5 v 1/t c t.b.d. 5.0 10.0 mhz 200 ns (typ.) frequency v cc 2.2 v 1/t c t.b.d. 5.0 8.0 mhz 200 ns (typ.) duty t ch /t c t.b.d. 0.5 0.6 ?? clock rise/fall t crf ?? t.b.d. ns ? ? 50.51 ? s cycle t h ? 252 ? clk 19.8 khz (typ.) display period t hd 240 clk ? front porch t hf 1.0 3.0 ? clk ? pulse width t hp 2.0 5.0 ? clk ? back porch t hb 2.0 4.0 ? clk ? t hp + t hb (quarter data function not used) 4.0 t.b.d. t.b.d. clk ? t hp + t hb (quarter data function used) 10.0 t.b.d. t.b.d. clk ? hsync setup time t hss t.b.d. ?? ns ? horizontal signal hsync hold time t hsh t.b.d. ?? ns ? ? 16.67 ? ms cycle t v t.b.d. 330 t.b.d. h 60.0 hz (typ.) front porch t vf 1.0 2.0 ? h ? pulse width t vp 1.0 5.0 ? h ? back porch t vb 1.0 3.0 ? h ? t vf + t vp + t vb 4.0 10.0 ? h ? vsync setup time t vss t.b.d. ?? ns ? vertical signal vsync hold time t vsh t.b.d. ?? ns ? clock ? data timing t dh t.b.d. ?? ns ? data data ? clock timing t ds t.b.d. ?? ns ?
preliminary product information s16269ej2v0pm 61 pd161831 serial interface ? ? ? ? serial interface between mcu and pd161831 (when scleg0 = scleg1 = h) sclk si lcdcs t css t csh t scyc t f t r t shw t slw t sds t sdh so t sdd t a = ? ? ? ? 40 to +85 c, v cc = 2.2 to 3.6 v, v s = 5.0 v 0.5 v, v ss = 0 v parameter symbol condition min. typ. note max. unit serial clock cycle t scyc 150 ns sclk_sub high-level pulse width t shw 60 ns sclk_sub low-level pulse width t slw 60 ns data setup time t sds 60 ns data hold time t sdh 60 ns t css 90 ns cs ? scl time t csh 90 ns sclk so output delay time t sdd t.b.d. ns note typ. values are reference values when t a = 25 c. remarks 1. the input signal's rise/fall times (t r and t f ) are rated as 15 ns or less. 2. all timing is rated based on 20 to 80% of v cc .
preliminary product information s16269ej2v0pm 62 pd161831 ? ? ? ? serial interface between pd161831 and back panel sclk_sub so_sub gcs, /cs1 cs2 t css2 t csh2 t scyc2 t f t r t shw2 t slw2 t sdd2 t a = ? ? ? ? 40 to +85 c, v cc = 2.2 to 3.6 v, v s = 5.0 v 0.5 v, v ss = 0 v parameter symbol condition min. typ. note max. unit serial clock cycle t scyc2 t.b.d. ns sclk_sub high-level pulse width t shw2 t.b.d. ns sclk_sub low-level pulse width t slw2 t.b.d. ns t css2 t.b.d. ns cs ? sclk_sub time t csh2 t.b.d. ns sclk_sub so_sub output delay time t sdd2 t.b.d. ns note typ. values are reference values when t a = 25 c. remarks 1. the input signal's rise/fall times (t r and t f ) are rated as 15 ns or less. 2. all timing is rated based on 20 to 80% of v cc .
preliminary product information s16269ej2v0pm 63 pd161831 timing requirements when not using timing generator t.b.d. timing requirements (t a = ? ? ? ? 40 to +85 c, v cc = 2.2 to 3.6 v, v ss = 0 v, t r = t f = 10 ns) parameter symbol condition min. typ. max. unit clock pulse width pw clk 100 ns clock pulse high time pw clk(h) 30 ns clock pulse low time pw clk(l) 30 ns data setup time t setup1 20 ns data hold time t hold1 20 ns start pulse setup time t setup2 20 ns start pulse hold time t hold2 20 ns start pulse low time t spl 3clk last data timing t ldt 2clk clk ? stb time t clk-stb clk stb 20 ns stb pulse width pw stb 40 ns start pulse rising time t stb-sth stb sth 3clk stb setup time t setup4 20 ns stb hold time t hold4 20 ns pol ? rsw_o time t pol-rsw t.b.d. ns ap pulse width (high power mode) pw aph t.b.d. s ap pulse width (low power mode) pw apl stb cycle = 40 s, c l = 30 pf t.b.d. s
preliminary product information s16269ej2v0pm 64 pd161831 [memo]
preliminary product information s16269ej2v0pm 65 pd161831 [memo]
preliminary product information s16269ej2v0pm 66 pd161831 [memo]
preliminary product information s16269ej2v0pm 67 pd161831 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
pd161831 reference documents nec semiconductor device reliability/quality control system (c10983e) quality grades on nec semiconductor devices (c11531e) ? the information contained in this document is being issued in advance of the production cycle for the device. the parameters for the device may change before final production or nec corporation, at its own discretion, may withdraw the device prior to its production. ? no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. ? nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, c opyrights or other intellectual property rights of nec corporation or others. ? descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. ? while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. ? nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m5 98. 8

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